qpl62 07 high - linearity sdars lna ds rev c subject to change without notice 1 of 7 www.qorvo.com product description the QPL6207 is a high linearity, ultra - low noise gain block amplifier in a small 2x2 mm surface - mount package. at 2332 mhz, the amplifier typically provides +3 4 dbm oip3. the amplifier does not require any negative supplies for operation and can be biased from positive supply rails from 3.3 to 5 .25 v. the device is housed in a lead - free/green/rohs - compliant industry - standard 2x2 mm package. the QPL6207 uses a high performance e - phemt process. the low noise amplifier contains an internal active bias to maintain high performance over temperature. functional block diagram feature overview ? high gain device C typical value 1 8.5 db ? ultra - low noise figure, 0. 4 5 db nf at 2332 mhz ? high linearity, +3 4 dbm output ip3 ? high input power ruggedness, >29 dbm pin, max ? unconditionally stable ? externally controlled icq with vbias ? integrated shutdown control pin ? 3 - 5 v positive supply voltage: ?vgg not required applications ? s dars active antenna ordering information part number description QPL6207 sb 5 piece sample bag QPL6207 sq 25 piece sample bag QPL6207 sr 100 piece 7 reel QPL6207 tr7 2500 piece 7 reel QPL6207pck - 01 evaluation board + 5 piece sample bag package: dfn, 8 - pin 2.0mm x 2. 0 mm
qpl62 07 high - linearity sdars lna ds rev c subject to change without notice 2 of 7 www.qorvo.com absolute maximum rat ings storage temperature - 65 to 150 c supply voltage (v dd ) +7 v rf input power, cw, 50,t = 25c +30 dbm electrical specifications at +25 ? c test conditions unless otherwise noted: vdd = +4.5 v, vbias = + 3.6v, temp=+25c, 50 system note: 1 ) noise figure data has input trace loss de - embedded 2 ) icq set by external 3.3k resistor parameter rating units parameter min typ max units supply voltage (v dd ) +3. 3 + 4.5 +5.25 v bias voltage (v b ias ) +3.3 +3.6 +5.25 v t case ? parameter conditions min typ max units operational frequency range 2320 2332 2345 mhz gain 17.5 1 8.5 20.5 db input return loss 9.5 db output return loss 8.5 db output p1db + 20 dbm output ip3 pout=+5 dbm/tone, 1 0. 4 5 0. 65 db power shutdown control (pin 6) on state 0 0. 63 v off state (power down) 1.17 3.3 v dd v current, i dd 2 on state 5 0 ma off state (power down) 3 4 ma shutdown pin current, i sd v pd 1.17 v recommended operating conditions
qpl62 07 high - linearity sdars lna ds rev c subject to change without notice 3 of 7 www.qorvo.com pin configuration and description pin no. label description 1 vbias sets the icq bias point for the device. 2 rf in rf input pin. a dc block is required. 6 shut down a high voltage (>1.17v) turns off the device. if the pin is pulled to ground or driven with a voltage less than 0.63v, then the device will operate under lna on state. 7 rf out / dcbias rf output pin. dc bias will also need to be injected through a rf bias choke/inductor for operation. 3, 4, 5, 8 nc no electrical connection. provide grounded land pads for pcb mounting integrity. backside paddle rf/dc gnd rf/dc ground. use recommended via pattern to minimize inductance and thermal resistance; see pcb mounting pattern for suggested footprint.
qpl62 07 high - linearity sdars lna ds rev c subject to change without notice 4 of 7 www.qorvo.com applications schematic vbias=3.6v icq 40ma 50ma 60ma 70ma 80ma vdd=4.5v r3 4.6k 3.3k 2.55k 1.9k 1.55k
qpl62 07 high - linearity sdars lna ds rev c subject to change without notice 5 of 7 www.qorvo.com mechanical information marking: part number C 6207 trace code C xxxx notes: 1. all dimensions are in millimeters. angles are in degrees. 2. except where noted, this part outline conforms to jedec standard mo - 220, issue e (variation vggc) for thermally enhanced plastic very thin fine pitch quad flat no lead package (qfn). 3. dimension and tolerance formats conform to asme y14.4m - 1994. 4. the terminal #1 identifier and terminal numbering conform to jesd 95 - 1 spp - 012.
qpl62 07 high - linearity sdars lna ds rev c subject to change without notice 6 of 7 www.qorvo.com pcb mounting pattern notes: 1. all dimensions are in millimeters. angles are in degrees. 2. use 1 oz. copper minimum for top and bottom layer metal. 3. vias are required under the backside paddle of this device for proper rf/dc grounding and thermal dissipation. we recommend a 0.35mm (#80/.0135") diameter bit for drilling via holes and a final plated thru diameter of 0.25 mm (0.10). 4. ensure good package backside paddle solder attach for reliable operation and best electrical performance.
qpl62 07 high - linearity sdars lna ds rev c subject to change without notice 7 of 7 www.qorvo.com product compliance information esd sensitivity ratings caution! esd - sensitive device esd rating: class 1b value: passes 500 v to < 1000v test: human body model (hbm) standard: jedec standard jesd22 - a114 esd rating: class c2 value: passes 500 v to <1000v test: charged device model (cdm) standard: jedec standard jesd22 - c101 msl rating msl rating: level 2 test: 260c convection reflow standard: jedec standard ipc/jedec j - std - 020 solderability compatible with both lead - free (260 c max. reflow temperature) and tin/lead (245 c max. reflow temperature) soldering processes. package contact plating: nipdau this part is compliant with eu 2002/95/ec rohs directive (restrictions on the use of certain hazardous substances in electrical and electronic equipment). rohs compliance this product also has the following attributes: ? lead free ? halogen free (chlorine, bromine) ? antimony free ? tbbp - a (c 15 h 12 br 4 0 2 ) free ? pfos free ? svhc free
|
